AMD Opteron vs. Intel Xeon: Database Performance Shootout
by Anand Lal Shimpi, Jason Clark & Ross Whitehead on March 2, 2004 2:11 AM EST- Posted in
- IT Computing
"Order Entry" Stress Test: Measuring Enterprise Class Performance
One complaint we've historically received about our Forums database test was that it isn't strenuous enough for some of the Enterprise customers to make a good decision based on the results.
In our infinite desire to please everyone we worked very closely with a company that could provide us with a truly Enterprise Class SQL stress application. We cannot reveal the identity of the Corporation that provided us with the application because of non-disclosure agreements in place. As a result, we will not go into specifics of the application, but rather provide an overview of it's database interaction so that you can grasp the profile of this application and better understand the results of the tests (and how they relate to your database environment).
We will use an Order Entry system as an analogy for how this test interacts with the database. All interaction with the database is via stored procedures. The main stored procedures used during the test are:
sp_AddOrder - inserts an Order
sp_AddLineItem - inserts a Line Item for an Order
sp_UpdateOrderShippingStatus - updates an status to "Shipped"
sp_AssignOrderToLoadingDock - inserts a record to indicate which Loading Dock the Order should be shipped from
sp_AddLoadingDock - inserts a new record to define an available Loading Dock
sp_GetOrderAndLineItems - selects all information related to an Order and it's Line Items
The above is only intended as an overview of the stored procedure functionality; obviously the stored procedures perform other validation, and audit operations.
Each Order had a random number of Line Items, ranging from one to three. Also randomized was the Line Items chosen for an order, from a pool of approximately 1500 line items.
Each test was run for 10 minutes and was repeated three times. The average between the three tests was used. The number of Reads to Writes was maintained at 10 reads for every write. We debated for a long while about which ratio of reads to writes to would best services the benchmark and we decided there was no correct answer... so we went with 10.
The application was developed using C# and all database connectivity was accomplished using ADO.NET and used 20 threads, 10 for reading and 10 for inserting.
So as to ensure that IO was not the bottleneck, each test was started with an empty database and expanded to ensure that autogrow activity did not occur during the test. Additionally, a gigabit switch was used between the client and the server. During the execution of the tests, there were no applications running on the server or monitoring software. Task Manager, Profiler, and Performance Monitor where used when establishing the baseline for the test, but never during execution of the tests.
At the beginning of each platform both the server and client workstation was rebooted to ensure a clean and consistent environment. The database was always copied to the 8 disk RAID 0 array with no other files present to ensure that file placement and fragmentation was consistent between runs. In between each of the three test the database was deleted, the empty one was copied again the clean array. SQL Server was not restarted.
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Jason Clark - Wednesday, March 3, 2004 - link
Pumpkin not really..my point is that we used a standard shipping opteron system. I'm not questioning that Opterons support DDR400 or that if you wanted to "tweak" out a server (which is rarely done) that you could. My point is that currently quad opterons are shipping with DDR333 (what we tested). I'm sure (as I said) that down the road ddr400 will be a reality for the boxed/packaged systems but obviously right now it is not. All 4 systems that were shipped to us all came with ddr33 not ddr400.L8r
Jeff7181 - Wednesday, March 3, 2004 - link
I'm surprised nobody has speculated about who the corporation was that helped do the testing.I'll speculate that it was newegg.com =)
Jeff7181 - Wednesday, March 3, 2004 - link
I 2nd #15 motion for pics =)DBBoy - Wednesday, March 3, 2004 - link
Taken from an artilce on the new 4MB L3 products.The new 3-GHz Xeon MP with 4 Mbytes of cache is listed by Intel as available for $3,692 each in quantities of 1,000.
Tessel8 - Wednesday, March 3, 2004 - link
Why do all of the benchmark results page refer to "Potomac" as the 2-way Xeon 3.2GHz processor. This is absolutely not correct (maybe you are refering to Prestonia?).Ex. The results are split up into two categories: 2-way and 4-way setups. Remember that the 3.2GHz Potomac based Xeon is only available in 2-way configurations and is thus absent from the 4-way graphs.
I believe only the last paragraph on the last page is the only one refering to the correct Potomac processor.
Pumpkinierre - Wednesday, March 3, 2004 - link
#30 Jason, Your statement would be in conflict with your previous server comparison article(http://www.anandtech.com/IT/showdoc.html?i=1935&am..."Just recently, the x48 parts were launched, and with them, the Opteron gained support for DDR400 memory. Support for DDR400 has trickled down to all members of the Opteron family, but only certain revisions of the CPUs support DDR400"
I certainly thought they released 4 new DDR400 opterons late last year, covering all configs. At any rate it is the 2way that is in question and you had 2way 533MHz Xeons so, by rights, you should have used opteron 248s as this would be what an customer interested in this configuration would buy. The price of these is half again of the 848 making them even more attractive:
http://www.amd.com/us-en/Corporate/VirtualPressRoo...
You had two 248s in that last server article but again used DDR333. The photo on Pg 2 showed one of the opterons as an "AM" revision which, you state in the article, qualifies for DDR400 support. Of course, if these cpus, DDR400 Reg. modules or enabled Mobo were not on hand then it cant be helped and as you say the DDR333 setup still shows the Xeon memory structural problem.
Sante
TrogdorJW - Tuesday, March 2, 2004 - link
Wow... given that the 533 FSB on the 2-way Xeons easily makes up for the difference in cache size, I'm amazed that Intel hasn't actually validated an 800 FSB Xeon solution. Then again, Intel is *SO* cautious with introducing advancements in technology, especially in the server/enterprise markets. Not only would they have to validate the faster CPU, but the motherboard and chipset validation would probably take them a year at least. (Who knows... they might be working on this as we speak.) Too bad the P4EE aren't dual-CPU capable (I think) - that would be interesting to see benchmarks. Not that any real corporation would dare to go that route, but still, interesting.It will be interesting to see what happens with the Nocoma cores (and later Potomac). The 1 MB L2 cache can help out in desktop applications and more or less overcome the longer pipeline, but on Xeons where you're already running 2 MB L3 cache, I don't know that it will be as useful. Then again, the 800 FSB will probably more than make up for the deeper pipeline.
Needless to say, Intel definitely has some work to do. I'm waiting for them to migrate the Pentium M (P6 core with improvements) back to the desktop. Heheheh....
lneves - Tuesday, March 2, 2004 - link
Can you guys share the "SQL Loader" benchmark tool and the scripts used?Thanks.
Jason Clark - Tuesday, March 2, 2004 - link
Grayswan, each proc had 1 gb as that is how it has to be configured.More thoughts on DDR400. After doing a bit more reading I've confirmed that most all quad opterons ship with ddr333 so our tests conformed to what was available at the time of testing. Testing something that isn't a standard shipping configuration doesn't help people making a buying decision now. Most all quad opterons won't be hand built by an organization, they will be ordered as complete systems. Maybe later on this year we'll see a shift to ddr 400 and we can run some numbers.
Examples:
http://www.swt.com/qo.html
http://www.appro.com/product/server_4144h_2.asp
Grayswan - Tuesday, March 2, 2004 - link
What was the memory organization on the opterons? All memory on 1 proc? 2 modules on each proc? Also the 4-way opteron diagrom on P.3 shows each proc only using 2 interconnects. I believe all 3 are used so the diagram should be "crossbar"ish.